The invention relates to a method for handling data between a clock and data recovery circuit and a data processing unit of a telecommunications network node of an asynchronous network, and to a bit rate adaptation circuit, a clock and data recovery system and a telecommunications network node which implement said method.
Typically, network node elements of communication networks structurally comprise an input port, a Clock and Data Recovery circuit, a bit rate adaptation system, a data processing system and an output port. The Clock and Data Recovery circuit, in charge of regenerating the data received at the input port and the clock at which this data was transmitted throughout the network, passes these two signals to a bit rate adaptation system which is in charge of transmitting the recovered data to the node processing stage (switching/routing) at a rate which is indicated by the local clock of the network node.
Within network node elements dedicated to synchronous transport (e.g. SDH/SONET), such bit rate adaptation systems comprise usually a first-in-first-out (FIFO) memory with read and write pointers which are controlled by two independent clocks, a local network node clock and a recovered data clock taken out from the input signals, respectively.
In synchronous networks, such as SDH/SONET, clock generation and distribution can be well controlled, as data signal timing is related to a single timing reference (i.e. global reference). Incoming data frames to the network node are written onto and read from the memory stack in a synchronous manner, that is, read and write pointers are triggered with independent clocks which run continuously and more or less synchronously. In U.S. Pat. No. 6,166,963 for example, a system is disclosed which comprises a FIFO memory stack, a write unit, a read unit and a first and a second synchronization circuit. The write unit is configured to add elements to the FIFO memory stack based upon a first clock domain, and the read unit is configured to read elements from the FIFO stack based upon a second clock domain. The first synchronization circuit is operationally coupled with the write unit and is configured to receive the write pointer and synchronize it to the second clock domain. The second synchronization circuit is operationally coupled with the read unit and is configured to receive the read pointer and synchronize it to the first clock domain.
On the other hand, new type of asynchronous networks introduce new requirements for network node internal subsystems. U.S. Pat. No. 6,278,718 although suited for another type of asynchronous communication, more specifically, distributed asynchronous networks, is seen as the closest state of the art concerning the present invention.